AnsweredAssumed Answered

ZedBoard ADV7511 can not display

Question asked by cenjd on Aug 17, 2015
Latest reply on Aug 22, 2015 by cenjd

hello!

      I am now building a 1080P HDMI display project on zedbord according to the wiki ADV7511 Xilinx Evaluation Boards Reference Design [Analog Devices Wiki]

I found that Audio portion is not necessary for ADV7511 according to the answer here https://ez.analog.com/message/122520#122520

So I removed the Audio IP core and DMA channel from Reference Design and disabled Audio relate code in .c files.

I am using vivado 2015.1.

After download hardware and software program, the screen display a full green. As below:

IMG_20150817_194540.jpg

 

I find an explanation of HDL IP core Registers here http://wiki.analog.com/resources/fpga/docs/hdl#building_on_vivado

So I print HDL cores register value .

CLKGEN REGs are from ClockGenerator (axi_clkgen) IP core.

HDMITXCORE REGs are from HDMI Transmit (axi_hdmi_tx) IPcore.

VDMA regs are from Xilinx VDMA IP core.

 

*****CLKGEN REG*****

0x00000040 is :0x00000003

0x0000005C is :0x00000000

0x00000070 is :0x004F8000

0x00000074 is :0x00028000

*****CLKGEN REG*****

*****HDMITXCORE REG*****

0x00000040 is :0x00000001

0x00000044 is :0x00000000

0x00000048 is :0x00000001

0x0000004C is :0x00000000

0x00000054 is :0x00017C57

0x00000058 is :0x00000001

0x0000005C is :0x00000001

0x00000060 is :0x00000001

0x00000064 is :0x00000003

0x00000400 is :0x07800898

0x00000404 is :0x00000058

0x00000408 is :0x086C00EC

0x00000440 is :0x04380465

0x00000444 is :0x00000005

0x00000448 is :0x04610029

*****HDMITXCORE REG*****

VDMA - Partial Register Dump (uBaseAddr = 0x43000000):

  PARKPTR          = 0x00010000

  ----------------

  S2MM_DMACR       = 0x00000000

  S2MM_DMASR       = 0x00000000

  S2MM_STRD_FRMDLY = 0x00000000

  S2MM_START_ADDR0 = 0x00000000

  S2MM_START_ADDR1 = 0x00000000

  S2MM_START_ADDR2 = 0x00000000

  S2MM_HSIZE       = 0x00000000

  S2MM_VSIZE       = 0x00000000

  ----------------

  MM2S_DMACR       = 0x00010003

  MM2S_DMASR       = 0x00011000

  MM2S_STRD_FRMDLY = 0x00001E00

  MM2S_START_ADDR0 = 0x02000000

  MM2S_START_ADDR1 = 0x02000000

  MM2S_START_ADDR2 = 0x02000000

  MM2S_HSIZE       = 0x00001E00

  MM2S_VSIZE       = 0x00000438

  ----------------

  S2MM_HSIZE_STATUS= 0x00000000

  S2MM_VSIZE_STATUS= 0x00000000

  ----------------

 

It seems the VDMA is OK.

Are there something wrong with ClockGenerator (axi_clkgen)  or HDMI Transmit (axi_hdmi_tx) ?

How can I fix the problem?

Thank you very much !

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