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AD9361 FIR overload problem

Question asked by gshadow on Aug 17, 2015
Latest reply on Sep 16, 2015 by tlili


While developing a wireless data exchange based on AD9361 (FMCOMMS3 board) and FPGA we faced a problem.

For testing purposes we trying to transmit DDS sine wave as well as some test data array using wired loop-back on antennas.

Without FIR there is clean sine wave received and test data received is almost good.

But when we trying to enable FIR all data is heavily corrupted, DDS sine wave looks more like some triangles and reading

0x5E register shows overloads starting from TFIR, RFIR and others (0xBF value).

We tried FIR coefficients calculated in MathLab for our configuration and default LTE 20 MHz ones, but looks like there is no difference.

Also we tried to read back coefficients to ensure it is programmed correctly.

We are using sampling frequency of 20 MHz and all half-bands enabled + FIR x2, which gives us x16 in total and 320 MHz ADC/DAC frequency.