I am using the Xilinx ZC706 eval card with an FMCOMMS2 and have downloaded the HDL code and compiled in Vivado after compiling all the libraries as detailed in the HDL instructions on the wiki site. The code compiles successfully and generates a bit file, however I am unable to load the bit file onto the hardware, getting this error of which I posted a screenshot
ERROR: [Labtools 27-1437] Failed to get a response from the Debug Core Hub on device xc7z045_1 .....
This is compiling the code as is, I have not made any HDL changes or added any ILAs to the design.
Any ideas what might cause this?