What interface clocking schemes do high speed DACs from Analog Devices use? What do I need to do to meet the data input timing?
There are mainly two interface clocking schemes in the high speed DACs, source synchronous + FIFO scheme and data clock out (DCO) + input data scheme.
The latest (and greatest) generation of high speed DACs (AD9122, AD9125, AD9148, AD9146 and etc) adopts the source synchronous scheme and features a FIFO to ease the interface timing. In source synchronous, a data clock in (DCI) is sent along with the input data from the data source such as an ASIC or FPGA. The input data is sampled by an internally generated clock in the DAC using the DCI as a reference. The PVT variation of the DCI tracks the variation experienced by the input data as they are from the same device. This advantage allows higher speed operation as compared to the traditional technique of providing a clock from the DAC device and receiving only data from the data source (the latter one above).
One issue of using source-synchronous clocking is the creation of a separate clock-domain at the DAC. The DAC clock-domain, i.e., the DACCLK, is often not synchronous to the DCI and thus to the internally generated input sampling clock. A FIFO stage is inserted between these two clock domains to ease the hand-off timing.
The previous generation of DAC products (AD9788, AD9779A, AD9783 and etc) uses the DCO+input data scheme. The data source takes the DCO as a reference clock and feeds the data to the DAC. The DAC samples the input data using an internally generated clock based on the DCO. The DAC features a fine delay line that allows the relative timing between this sampling clock and the input data to be adjusted so the input data can be correctly sampled.
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