Hello to anyone!
I am using 5 AD5544 DACs to get a total of 20 16-bit channels.
The analog output configuration is set for +/-10V similar to the description in the datasheet.
The DACs SPIs are connected in parallel with their CLK, /CS, /LDAC and /RESET lines while each DAC has it's own DATA line for faster update instead of daisy-chain.
The SPI signals are generated by a Spartan6 FPGA synchronous to the 20MHz clock:
CLK: 20MHz (50ns cycle, 50% duty)
DATA, /CS, /LDAC are synchronous to falling edge of CLK because DATA is shifted in and registers are updated on rising CLK edge.
/LDAC sequence is done at the end of all four channel transfers to update all outputs at the same time.
00+DATA0 * /CS cycle * 01+DATA1* /CS cycle * 10+DATA2 * /CS cycle * 11+DATA3 * /CS cycle * /LDAC cycle
I have sporadic 0V analog outputs on channel 0 of each of the five DACs. Sporadic means one per minute or hour or day.
It is only on channel 0 and not on 1, 2 or 3
It is not at the same time on the five DACs but it is on every DAC
It happens more often if I connect a oscilloscope probe (20pF) to /CS line and therefore it looks like a timing problem
Reducing CLK to 10MHz or 5MHz didn't make a difference therefore it seems to be an edge detection problem
Does anybody had similar effects with the AD5544?
Could it be a problem having /CS, CLK and /LDAC connected in parallel to the same FPGA output?
Thanks for any ideas on this behavior.