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EVAL-AD5761R: Correct clock input procedure?

Question asked by AnCorx42 on Aug 11, 2015
Latest reply on Aug 13, 2015 by AnCorx42



New to using this EVAL-AD5761R device so I am hoping for assistance.


The datasheet says that the device samples up to 50MHz and we'd like to test among a list of update rates. We've connected to SCLK and fed a 1V, 1Mhz signal from a signal generator. It does appear that we're affecting the DAC output, but I want to make sure that we aren't doing something wrong trying to control the update rate.


Please advise?