I have a large FPGA design in Vivado 2014.4 and also in 2015.2 that I have been working with. Unfortunately, due to numerous reasons, I cannot downgrade the design to 2014.2. Is there somebody that can help offer some suggestions for debugging and getting the design working in a later version? So far, I can run a design in 2014.2 and load it in a later version. For some reason, the following lines all return 0x00.
xil_printf("AD9467 CHIP ID: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_ID));
xil_printf("AD9467 CHIP GRADE: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE));
xil_printf("AD9517 CHIP ID: 0x%02x", ad9517_read(AD9517_REG_PART_ID));
AD9467 CHIP ID: 0x00
AD9467 CHIP GRADE: 0x00
AD9517 CHIP ID: 0xD3AD9467[0x016]: 00
adc_delay: setting zero error delay (14)
I basically took the reference design from GitHub, deleted everything that I wasnt using, and re-synthesized the design. It worked. I then took the design and loaded in a later version and that is when the SPI seemed to stop.
Thank you for your help.