Can the ADV7619 support this portrait resolution 1080 x 2880, 60Hz?
Do you mean 1800x2880?
No, I mean 1080x2880.
Do you have some information on this resolution? Do any of the HDMI test generators support it?
We are working with a prototype display, which is the reason for the odd resolution.
I am checking if there are any generators that can support this custom resolution.
For now, we will be using a PC to drive the output.
However, in general can the ADV7619 support this?
Does it use the embedded syncs to generate the timing and extract the pixel data?
Is this a VESA standard? Do you have the timing specifications?
No, this isn't a VESA standard. I am trying to get the timing specs.
Are there any limitations/constraints on the ADV7619 with regards to the timing?
The most important specification is the pixel rate. The ADV7619 can only handle formats/resolutions with pixel rates up to 300 MHz.
Keep in mind the LLC clock is limited to 170MHz. If you go above this you can go double wide output and run at 1/2 the pixel clock rate to be able to output 3G video
The pixel clock will be less than 300 MHz, it should be around 200 MHz.
So, just to confirm, will the ADV7619 be able to receive the format?
In general, if the pixel clock requirement is met, can the ADV7619 receive any format?
There may be other odd resolutions that I will need to support.
If the pixel clock is 172 MHz then you need to use double wide pixel bus and run LLC at 86 MHz.
Here are the timing specs:
Pixel clock: 216 MHz
V Blanking: 42 lines
V Active: 2880 lines
H Blanking: 152 clocks
H Active: 1080 clocks
Since the pixel is more than 170 MHz, you're going to need to bypass the DPP and CP modules. Please refer to the section called "Pass Through Mode" in the ADV7619 hardware manual.
Are you sure you all can get a PC to output this mode over HDMI? And you can verify this on an HDMI analyzer?
Yes, we can get a PC to output this mode. Also, we have a HDMI test generator where we can load custom video timing.
I have another question that is sort of related. In addition to supporting the 1080x2880 timing from a HDMI source, I have a test case where the source will be dual link DVI.
In this case only half of the horizontal active portion will be sent on each link, however, do know if the horizontal blanking is also reduced by half? And if the pixel clock is also reduced by half?
It might be easier to test this using your HDMI generator since it likely will not require EDID information in order to output this mode.
You will need to use the ADV7619's "pass through mode" in order to receive this signal and you will need to use the 48-bit interface in order to output it. You could use our ADV7619 evaluation board and a logic analyzer connected to the ADV7619 output pins.
Please note that the ADV7619 does not support dual link DVI:
I am starting to test with the 1080x2880 timing mode using a PC.
I just want to double check a couple of things:
1. I am using these 4K2K settings:
:4kx2k 444 upper part of bus:
50 10 6F ; PATH B- SPECIAL 2kx2k upper 24 bit. PATH A=ALL CHANNELS DISABLED
50 19 20 ; ADV7619 4kx2k mode. SYNC REGEN DISABLED
50 11 00 ; VIDEO PATH B=TMB TO TMB
50 1A 0F ; VIDEO PATH SELECT=PATH B OUTPUT CLOCK CONTROL, PATH B DATA TO DACS, AV0, AV1
98 FF 80 ; I2C reset
98 F4 80 ; CEC
98 F5 7C ; INFOFRAME
98 F8 4C ; DPLL
98 F9 64 ; KSV
98 FA 6C ; EDID
98 FB 68 ; HDMI
98 FD 44 ; CP
50 20 00 ; De-assert HDP
68 C0 03 ; ADI Recommended Write
98 01 06 ; Prim_Mode =110b HDMI-GR
98 02 F2 ; Auto CSC, RGB out, Set op_656 bit
98 03 54 ; 2x24 bit SDR 444 interleaved mode 0
98 05 28 ; AV Codes Off
98 06 A0 ; No inversion on VS,HS pins
98 0C 42 ; Power up part
98 15 80 ; Disable Tristate of Pins
98 19 83 ; LLC DLL phase
98 33 40 ; LLC DLL MUX enable
98 DD A0 ; LLC Half frequency
4C B5 01 ; Setting MCLK to 256Fs
4C C3 80 ; ADI recommended writes (HiFreq)
4C CF 03 ; ADI recommended writes (HiFreq)
68 3E 69 ; ADI reccommended writes
68 3F 46 ; ADI reccommended writes
68 4E 7E ; ADI reccommended writes
68 4F 42 ; ADI reccommended writes
68 02 03 ; ALL BG Ports enabled
68 57 A3 ; ADI reccommended writes
68 58 07 ; ADI reccommended writes
68 83 FC ; Enable clock terminators for port A & B
68 84 03 ; FP MODE
68 85 10 ; ADI recommended setting
68 86 9B ; ADI recommended setting
68 89 03 ; HF Gain
68 9B 03 ; ADI recommended setting
Are these settings suitable for the 1080x2880 timing?
2. You mentioned using pass-through mode, but according to the HW user guide if the 48bit interface is used then CP_COMPLETE_BYPASS_IN_HDMI_MODES is disabled. So, does that mean the ADV7619 is not in pass-through mode?
Note that I am receiving RGB888 and outputting RGB888.
I think I meant bypass mode rather than pass through mode.
Can you provide this signal into an HDMI analyzer and let us know the specs?
Sorry, what is bypass mode?
Here are the specs of the 1080x288 timing:
I guess the term "bypass mode" isn't used in our documentation.
Please refer to the ADV7619 Reference Manual, Rev C, page 106:
Therefore HDMI video with pixel clock frequencies above 170 MHz must be routed directly to Video Output Formatter bypassing Data Preprocessor (DPP) and Component Preprocessor (CP). For more information about bypassing DPP and CP please refer to Pass Through Mode section.
I believe you can bypass the DPP by setting DPP_BYPASS_EN to 1 and you can bypass the CP by setting CP_COMPLETE_BYPASS_IN_HDMI_MODE to 1.
Please refer to the latest scripts and latest required settings document in the ADV7619 design support files FAQ:
ADV7619 Design Support files
I will try bypassing the DP.
However, for CP, according to the HW guide when 2x24bit SDR 444 interleaved is used CP_COMPLETE_BYPASS_IN_HDMI_MODE should be disabled ( IO MAP, Register 0xBF = 0).
But for pixel clocks > 170 MHz, CP is to be in bypass mode.
Which statement is correct?
Also, the HW guide states that the LLC clock should be half freq (IO Map, Register 0xDD = 0xA0).
But in ADV7619-VER1.8c.txt, IO Map Register 0xDD = 0x00.
Which is correct?
Note that I am using an ADV7619 device from 2012, so my register programming is based on the
ADV7619-VER1.2c.txt and ADV7619_RecSettings_1-4.pdf.
Would there be any issues using the latest settings with my older hardware?
The latest ADV7619 settings are required if your pixel clock is greater than 148.5MHz. This is regardless of the date code on your ADV7619.
Which configuration script are you referring to in ADV7619-VER.1.8c.txt?
The pixel clock for the timing I provided in a previous message is 216MHz.
I am referring to this script: :03-03 YCbCr 444 In - 2x24-bit YCbCr 444 Out - For use up to 4k2k:
However, for my application I am using RGB in and out.
From the HW guide it states that:
CP_COMPLETE_BYPASS_IN_HDMI_MODE should be 0 when using 2x24bit SDR. But it also states that for pixel clocks > 170MHz CP_COMPLETE_BYPASS_IN_HDMI_MODE should be 1.
Also, the HW guide states the when in 2x24bit SDR, the LLC should be programmed to half freq (IO Map, Reg. 0xDD = 0xA0). But in the script it has IO Map, 0xDD = 0x00.
I will update my code to use the latest settings, however, can you please clarify the above.
If you want RGB out, I think you should be using the following script:
:03-01 RGB 444 In - 2x24-bit RGB 444 Out - For use up to 4k2k:
The reason for the discrepancy on IO map 0xDD is due to the fact that the ADV7619 scripts and required settings document have been recently updated (like last week) whereas the ADV7619 HW Guide has not. I will make sure the ADV7619 experts are aware of this discrepancy, though.
Please use the settings in the ADV7619 scripts and required settings document.
Thanks I missed the 03-01 script. I will use it.
To clarify, is the LLC clock half freq or full freq when IO Map Reg. 0xDD = 0x00?
Also, what about CP_COMPLETE_BYPASS_IN_HDMI_MODE?
Can I enable bypass if the pixel port is set to 2x24bit RGB 444 (IO Map, Reg. 0x03=0x54)?
Are you using the ADV7619 evaluation board or a custom board?
I am using my custom board.
On pages 26, 203, and 152 of the ADV7619 reference manual, we seem to be saying that CP_COMPLETE_BYPASS_IN_HDMI_MODE needs to be set to 0.
Furthermore, the power-up setting of this register is "0" and our scripts are not setting it.
However, the description of this register on page 152 of the reference manual seems to be saying that 1 is bypass and 0 is normal.
I'm working with the ADV7619 experts to clarify the description and setting of this bit for use up to 4k2k.
Thanks for helping me clear this up.
A couple of other things I would also like to get clarified:
1. Is LLC clock half rate based on the latest settings? It seems not.
If that is the case, if the pixel port is 2x24bit 444 does that mean the the line length from the ADV7619 is half?
e.g. For 1080p60, is HS asserted every 1100 clocks instead of every 2200? Likewise, is DE asserted per line for 960 clocks instead of 1920?
2. It looks like DPP_BYPASS is in bypass as the default. Is that correct? If so, then I don't need to touch this control.
On Q1, I think the LLC will have to be half the pixel clock rate. We split the pixel data across two buses for the purpose of lowering the LLC frequency to a frequency less than 150 MHz. I don't think any settings we could publish will change this fact. I would suggest you purchase an evaluation board and look at the LLC frequency when running a script like 03-01 (RGB 444 In - 2x24-bit RGB 444 Out - For use up to 4k2k).
On Q2, it does appear that DPP_BYPASS_EN is set by default.
Thanks for the answers.
I tried with my board and LLC clock is indeed half rate when using the latest settings.
So, the only outstanding questions is how CP_COMPLETE_BYPASS_IN_HDMI_MODE should be programmed
in 4K2K (or specifically, when 2x24bit 444 SDR is used).
I received the following response from the design team:
For double bus output modes (such as 2 x 24-bit output mode used in 4K operation), the CP core is automatically bypassed. You don’t need to set the CP_COMPLETE_BYPASS_IN_HDMI_MODE bit in 2 x 16/20/24-bit output modes.
I hope this helps!
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