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AD7762 : Settling time after disabling PD

Question asked by ysuzuki on Aug 10, 2015
Latest reply on Oct 29, 2015 by jcolao

Hello,

 

I have a question about AD7762 from our customer.

AD7762 is consist from delta-sigma modulator and it has latency of digital filter.

The customer is using followings cofiguration and condition.

 

[Configuration]

1. CDEV=1, OCLK = MCLK

2. Filter 1 : 4x

   Filter 2 : 8x

   Filter 3 : Bypassed

3. PD : 0

4. LPWR : 0

 

 

[Condition]

1. Input level is DC. (mostly constant levels)

 

 

[Start-up sequence after powered on]

1. H/W reset.

2. Write 0x0022 to Control Register2.

3. Write 0x000B to Control Register1. (PD:0, LPWR:0)

4. Data reading starting.

 

The customer says,

  In spite of constant DC level input, the data has a long transient time to become stable.

  It is needed about 540us to become stable.

 

The timing specification by this filter configuration is followings,

ICLK    Filter1  Filter2  Filter3         Computation  Filter   Pass-Band   Output Data

Freq.                                               Delay       Delay    Bandwidth     Rate (ODR)

20MHz      4x       8x    Bypassed      2.6us      10.8us   140.625kHz    625 kHz

 

The expected latency is 2.6us + 10.8us = 13.4us

The transient time of the data is more than 500us longer than filter latency.

The customer is asking us how much time is needed to settle after disabling Power Down mode.

 

Could you please teach me the settling time after disabling PD ?

If you need more information, please let me know.

 

Best regards,

ysuzuki

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