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ADV7842 PLL_DIV_RATIO

Question asked by igalkroyter on Aug 11, 2015
Latest reply on Aug 19, 2015 by mattp

Hi,

 

We are configuring the ADV7482 to sample non-standard video utilizing the Component Processor.

 

Among all registers we are setting the PLL_DIV_RATIO register to the number of "pixels" (two 8-bit values per pixel) per line and sampling the output by an FPGA.

 

It seems like, for any value that we set the register, the number of pixels is less by 4 (i.e. setting the value to 1584 receiving 3160 8-bits, that is 1580 pixels ; setting 1580 receiving 3152 8-bits, that is 1576 pixels).

 

Please advise.

 

Igal Kroyter

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