I am working on AD9364. BBPLL VCO calibration and RF synthesizer charge pump calibration is done. But RF synthesizer VCO calibration is not done. The register 0x247 =0x40(PLL lock bit is 0 and the CP Ovrg Low is 1). The register 0x287=0x80(PLL lock bit is 0 and the CP Org High is 1)
1) Is CP Ovrg high/low is the reason for PLL Lock state?
2)What CP Ovrg high /low means?