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ADF4106- Lock detect - Freq drift calculation

Question asked by FreddyS on Aug 6, 2015
Latest reply on Aug 12, 2015 by rbrennan

 

Hello

I am using the ADF4106 and noticed that the digital lock detect  is not  going down as expected  when the pll is not locked .

  But I get a lock detect  signal with duty cycle of  ~ 50 % ,  not going to zero as seen below !

My setup :

Ref freq =10 MHz

Pdf  freq = 10 MHz  [ r dev = 0]

Output freq = 4.9 GHz

   

freq drift is from 5 to 20 MHz

 

   

 

 

From the data sheet  I understand that  up to 4MHz  the LD is “1”  [ in our setup ]

 

Please advise if my calculation below are right.

 

How should I calculate the freq drift to keep the  lock detect at “1”    , sw on/off range   and going to a steady “0” .

 

Divider R = 1  [ 10MHz]  = 100 nSec

 

3 cycles with phase error < 15 nSec =  LD            15% ??

 

Phase error >  25 nSec  = unlock        40%  ??

 

Thanks

 

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