How many I2S data bits are used to transmit 20 bit PCM data? Can anybody tell?
I2S supports 8/16/32bits.
The data sheet does appear a little vague on this point:
However, we can safely assume that the I2S format in question is 32-bit. The timing diagram gives it away -- showing that after the 20 data bits, there's some unused bits that of the standard I2S choices, could only add up to 32:
The ADAU7002 will automatically detect the ratio between LRCLK and BCLK. For 2-channel I2S the minimum is 64x LRCLK which translates to 32 BCLK cycles per channel. If you are using TDM and have more than two channels then the BCLK and LRCLK signals must have 32 BCLKs per channel and the 7002 will automatically detect how many slots there are in the signal. Should you configure the slots driven to be higher than the number of slots in the signal driving the 7002 then you will not see any output.
So if the BCLK is 64 x LRCLK it will know it is TDM2 (I2S). If the BCLK is 128 x LRCLK then it knows there are four TDM slots each with 32 bits of bit clock.
What is the difference between SDATA TDM Mode and SDATA I2S justified Mode.?
How to config between these 2 modes ?
Do I see 20 Cloclk data in both modes ?
Part of the configuration is automatic and part is done with the configure pin.
Table six shows you the configure pin settings. This selects which slot the audio will be placed and the unused slots will tri-state.
It will know the number of TDM slots by comparing the difference between the LRCLK and the BCLK that is being sent to it. Should you set it up in an invalid way it will either no produce any output or place the audio data in a slot you did not intend. The data will always be 20 bits and the slot length needs to be 32 bits per channel.
Good afternoon Dave,
I have some questions when using ADAU7002. Can you please help me to make them clear?
1. How many BCLKs per channel (Left or Right) if I configure ADAU7002 issue I2S Data format? I assume that 32 BLCKs per channel or 64 BCLks per cycles in LRCLK line.
2. In SDATA line (Figure 14 - page 11 in datasheet), I see there are some delays before "20 BCLKs" data bit. How many delayed BCLKs before 20 BCLKs data bit? Base on what I read in this topic "How many BCLK need to be generated for SDATA for every LRCLK in SDATA TDM mode and SDATA I2S justified mode ", TylerK said that they (20 BCLKs data bit) would be just delayed from the start of the LRCLK by one BCLK. Please refer to my attached image for more details.
Can you please verify what I understand about ADAU7002 are correct? Thank you.
I2S is where there is one BCLK delay after the LRCLK transition.
I2S also has 32 BCLK's per channel, so 64 BCLK transitions per frame.
The ADAU7002 will output 20 bits so 20 of the 32 bit clocks are for data and the remaining 12 the sdata pin will tri-state.
The data for the right channel is also delayed by one BCLK.
Everything is slid over by one BCLK.
ADAU7002 will output 20 bits data for example received data is "0xABCDE". How to save the last 4 bits data into memory? I want to save data from ADAU7002 to SD card byte by byte.
1. Save: "0xAB"(1 byte), "0xCD" (1 byte). The last 4 bits "0xE" will be save as "0x0E" or "0xE0"
2. Save: "0x0A"(1 byte), "0xBC" (1 byte) "0xDE".
Which way is correct? Thank you.
I would save it as a 24-bit number with the last four bits as zero. This way the sign bit is in the proper place and I would think that most other software and hardware you send the data to will be 24 bit devices anyway.
So 0x AB CD E0
Is it possible to change the word length from 32 (16bits + 12bits of 0's) to 16. I want to mux 4 PDM mics output into a single i2s output. However the receiver can only receive 32-bit words on high/ low of LR clock or word clock and hence want to see if there is any way of reducing the word length to 16.
No you cannot change the slot size but there may be a solution. I do not know your processor's capabilities but there is a creative solution. (I am going to make up sample rate for this example) If you can send out the frame clock at 48kHz fs and the BCLK at 6.144MHz and let all the 7002's stuff their data into a TDM4 stream. So then all you need to do is clock in the data using a 96kHz frame clock that comes from the same clock source as the 48K clock so they are in sync. Then the serial port will think it is stereo data and pick up the first two slots and on the next 96kHz cycle slots 3 and 4 will be picked up. Then internally you assemble the data and process all four channels at 48kHz rate.
The way to do this would be to use two ports, one setup to produce Frame Clock and Bit clock at the 48kHz rate and send that to the 7002's. Then the SDATA from the 7002's need to feed a different serial port input. This serial port would be set to 96kHz fs but the clocks do not go anywhere except internally to drive the shift registers to shift in the data.
I have done tricks like this in our parts and it works great.
Is there an email I can reach you at. I wanted to share a block diagram and wanted to get your feedback.
Wanted to know a simple external clock divider from 96khz to 48khz would work or would cause phase difference between LR Clock and Bit clock.
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