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BF518F16 cache init

Question asked by mantur on Aug 6, 2015
Latest reply on Aug 26, 2015 by gvasanth

I developed a board based on BF518F16 with 64Mbyte SDRAM and 8Gbyte NAND.

core2.jpg

All work fine, but would like to know where can I find a document or an example code where explained the cache initialization and usage.

I use the GNU toolchain with a homebuilt environment:

Blackfin GNU Toolchain - D.T.A.

In a simple SDRAM speed test I achieve a performance of 170 Mbyte/s in writing and 30 Mbyte/s in reading.

Can be these value increased with a correct cache initialization?

Regards

Manuele

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