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AD9361 FB_CLK

Question asked by cy92612 on Aug 5, 2015
Latest reply on Aug 6, 2015 by CsomI

Is it a bad idea to use a MMCM/PLL in the Xilinx FPGA to adjust the internal clocking and FB_CLK output by the FPGA? In a previous design, I used only a clock buffer to loop back the FB_CLK from the DATA_CLK.  All I/O timing specs were met through tuning internal IDELAY and ODELAY elements in the FPGA.  However, in the current design, the interface (LVDS) is running at double the previous frequency, and a PLL solution made it easier to achieve timing closure.  But, for some reason in this new design, the EVM measurements are showing much worse numbers. I'm suspecting the fact that PLL generated FB_CLK has more jitter than a simple loopback.  I'm not sure how FB_CLK is used inside the AD9361, so there could be other issues as well.  Is that true?

 

Thank you for any help,

CYoung

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