I like to use the AD9524 as a low jitter (~150fs) 1GHz generator.
I could find in the datasheet a reference design for clock generator (I only found reference designs for clock cleaners...).
I like to connect XO to OSC input and not to use PLL1 (REFA/REFB inputs are not connected).
Is this configuration is ok?
How can I simulate the output jitter? (I couldn't simulate this configuration with ADISIMCLK)