AnsweredAssumed Answered

AD9910 messy signal when using PLL

Question asked by Hobbes on Aug 3, 2015
Latest reply on Aug 4, 2015 by Hobbes

Hi, i've been working with the AD9910 board and in establishing a PLL my signal has become less than clean.

I'm providing it with a 32MHz signal and setting the registers as follows:

CFR1: 0x00, 0x00, 0x00, 0x00 (unchanged)

CFR2: 0x00, 0x40, 0x08, 0x20 (unchanged)

CFR3: 0x15, 0x38, 0x41, 0x3c


I believe my math is correct and this should yield a system clock of 960 MHz, with a VCO range chosen that encompasses this value. And then my expected Sync_Clk output should be 1/4 of this, so 240 MHz. However the signal on my oscilloscope was all over the place so I looked at it on a spectrum analyzer and here's what it looks like:


It's not being resolved to a single frequency that is for sure, though there is a spike at 240 MHz, its just accompanied by many others. I'm at the highest value for the charge pump in the PLL, and this yielded the "best" result, lower values were increasingly messy. To be honest I do not know the internal function of the charge pump in a PLL, so if this is the issue it would be hard for me to find out.


Any and all help appreciated