AnsweredAssumed Answered

IODELAYCTRL issue with multiple axi_ad9361 cores using the same IO bank

Question asked by chrislogic on Jul 29, 2015
Latest reply on Aug 4, 2015 by chrislogic
Branched from an earlier discussion

Hi Lars,

 

I am working on a multi AD9361 design using a Zynq 7030. The design currently has 2 AD9361 devices and each has its PCORE_IODELAY_GROUP value configured for a different group. The error that I am getting does not seem to make sense as Vivado 2014.2 is complaining of incompatible standards of LVDS and LVDS.

 

Incompatible Pair of IO Standards: LVDS and LVDS

The following  terminals correspond to these IO Standards:

SioStd: LVDS       VCCO = 1.8 Termination: 0  TermDir:  In   IdelayId: 2 Bank: 34 DiffTermSet Placed LVDS :

  Term: rx_data_in_b_p[3]

  Term: rx_data_in_b_n[3]

  Term: rx_data_in_b_p[4]

  Term: rx_data_in_b_n[4]

  Term: rx_data_in_b_p[5]

  Term: rx_data_in_b_n[5]

  Term: rx_frame_in_b_p

  Term: rx_frame_in_b_n

SioStd: LVDS       VCCO = 1.8 Termination: 0  TermDir:  In   IdelayId: 1 Bank: 34 DiffTermSet Placed LVDS :

  Term: rx_data_in_p[3]

  Term: rx_data_in_n[3]

  Term: rx_data_in_p[4]

  Term: rx_data_in_n[4]

  Term: rx_data_in_p[5]

  Term: rx_data_in_n[5]

  Term: rx_frame_in_p

  Term: rx_frame_in_n

 

Do you have any advice on Zynq / IO-Delay block on different banks?

 

Regards

Chris

Outcomes