Do you have common mode rejection ratio (CMRR) data available for the AD9653? I assume this varies with both frequency and input level. Any reason this is not typically listed in datasheets for differential input ADCs? Thanks!

Do you have common mode rejection ratio (CMRR) data available for the AD9653? I assume this varies with both frequency and input level. Any reason this is not typically listed in datasheets for differential input ADCs? Thanks!

Les,

I'm not in the ADC group, but a lot of the ADCs, regardless of speed, require that the differential voltages

be centered on some voltage, usually VSY/2 or VREF/2. Part of it is a design consideration inside, but

from a practical point of view, if you are too far away from the midpoint, you are giving up dynamic range.

The AD9653 data sheet does mention something about this on page 21 of the rev. A data sheet.

See figures 52 and 53.

Harry

Thanks for your response Harry. Those graphs show SNR / SFDR vs DC common mode, so not quite what I'm after. The situation I'm asking about is when both inputs have the same AC input signal on them (rather than pure differential AC). The converters will - I assume - capture that common mode AC input as if it were a differential mode AC input at a reduced level given by the CMRR. This situation can arise when external signals couple equally onto both ADC inputs.

FYI: the datasheet I got from the web is now at rev B

Hi Les,

We addressed this question offline. If it is OK with you, I'll consider this topic/thread closed.

Thanks again.

Doug