we have one ADP1051 eighth brick demo board, with 470uf output capacitance and 48Vin, no load ,the output is not very stable like attached; why?
Hi Jun Yin,
It is a stable output and you can verify this by looking at a zoomed in version of the PWM falling edge for example OUTA which having the scope triggered on the rising edge. Additionally you can confirm this by doing a bode plot to verify the stability.
What now you are seeing is the quantization noise of the HF ADC that directly affects the output ripple. Remember that it is a sigma delta ADC (25MHz) and quantization is bound to occur.
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