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A9122 FPGA Library Example MMCM clock settings

Question asked by wmaguire on Jul 30, 2015
Latest reply on Aug 3, 2015 by larsc

Hi There,

 

I have been studying the axi_ad9122 reference design as a guide for integration of the AD9122 into a FPGA design.  My question concerns the MMCM clock setting defined in the module ad_serdes_clk.v, in particular the frequency of resulting div_clk used to clock the OSERDESE2 components.

 

  parameter   SERDES = 1;

  parameter   MMCM = 1;

  parameter   MMCM_DEVICE_TYPE = 0;

  parameter   MMCM_CLKIN_PERIOD  = 1.667; // ClkIn = 600MHz  approx

  parameter   MMCM_VCO_DIV  = 6;               // D

  parameter   MMCM_VCO_MUL = 12.000;      // M

  parameter   MMCM_CLK0_DIV = 2.000;        // O0

  parameter   MMCM_CLK1_DIV = 6;              // O1

 

 

Using the equation 3-2 on page 70 of UG472  I work out mmcm_clk_0 = 600 * M/(D*O0) = 600MHz.

Similarly mmcm_clk_1 =  600*M/(D*O1) = 600 *12/(6*6) =  200MHz.

 

Now looking at the instantiation of the ad_serdes_out in the module axi_ad9122_if.v we see

 

ad_serdes_out #(

    .DEVICE_TYPE (PCORE_DEVICE_TYPE),

    .SERDES(PCORE_SERDES_DDR_N),

    .DATA_WIDTH(16))

  i_serdes_out_data (

    .rst (dac_rst),

    .clk (dac_clk),

    .div_clk (dac_div_clk),

    .data_s0 (dac_data_i0),

    .data_s1 (dac_data_q0),

    .data_s2 (dac_data_i1),

    .data_s3 (dac_data_q1),

    .data_s4 (dac_data_i2),

    .data_s5 (dac_data_q2),

    .data_s6 (dac_data_i3),

    .data_s7 (dac_data_q3),

    .data_out_p (dac_data_out_p),

    .data_out_n (dac_data_out_n));

 

Essentially the ad_serdes_out is presented with 8 16 bit words, where each bit is taken in the order i0,q0,i1,q1,i2,q2,i3,q3.

 

In the module ad_serdes_out a generate block is used to create 16 data OSERDESE2 components.

 

The OSERDESE2 components are configured for DDR resulting in 2 data bits clocked per mmcm_clk_0.  This would mean that the parallel interface would need 4 * mmcm_clk_0 clocks before loading the next parallel data to be clocked out.  

 

As such I don't understand why the MMCM_CLK1_DIV = 6.  Should it not be 8 which would result in a mmcm_clk_1 of 150 MHz =  to 1/4 of the sample rate which would agree with packing 4 I/Q pairs for TX.



Regards



Walter

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