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how to get continuous  data with ad9361

Question asked by work_for on Jul 29, 2015
Latest reply on Aug 5, 2015 by work_for

Hellow, I am using ZEDboard and fmcomms3 for demodulation, and I need to get continuous data with a constant rate. I have generate the hdl project, and configure ad9361 with no-os system . I changed the data rate to 20M, which used the follow code :

{1280000000, 160000000, 80000000, 40000000, 20000000, 20000000},//uint32_rx

{1280000000, 80000000, 80000000, 40000000, 20000000, 20000000},//uint32_tx

And the adc port of the project is this :

1.png

I used fifo to interface dac port with my logic which said here. http://wiki.analog.com/resources/fpga/docs/hdl. The fifo is generate by vivado ip. The code is as fllow :

 

fifo_generator_0 Inst_fifo_generator_0(

.rst(rst_fifo),

.wr_clk(l_clk),

.rd_clk(my_clk),

.din(adc_data_i0),

.wr_en(adc_valid_i0),

.rd_en(my_rd),

.dout(my_data),

.full(full_fifo_0),

.empty(empty_fifo_0)

);

my_clk is 20MHz, my_rd is valid when the fifo is not empty.

But the result is sometimes i  get the empty signal valid, thus the my_data is not continuous, which is as fllows :

1.png

I have tried to use two fifo, but the data is still not continuous, because I have to wait for some time until the fifo is almos_full.

So is there anyone tell me what’s wrong with my design, is the config of ad9361 is wrong? Here is my configure code of ad9361. Plese help me.

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