How do I interface to multiple AD719x ADCs over the same serial interface ?
A single microcontroller can be used to communicate with several AD719x devices. The input of the ADC can be used to enable or disable the serial interface of the ADC. By controlling the inputs to the ADCs using a decoder, the microcontroller can communicate with each ADC individually or simultaneously. The figure below shows the interface between a microprocessor and several ADCs. The input of each ADC is connected to the decoder. Using the decoder, the microprocessor can select the ADC with which it wants to transfer data/instructions. When is high, the serial interface of the ADC is disabled and it ignores any activity on the data bus. To communicate with the ADC, its line can be taken low. The ADC will then have access to the data bus between itself and the microprocessor. The datasheet should be consulted for timing specifications.
something is not well understood in your schematic
how comes the Dout pins of the three ADCs shown are at one node ?
so how the controller will quite understand the difference between them ?
When /CS is high on the AD719x ADCs the DOUT pin is tri-stated. This means that it is not driven. In the above configuration the decoder will only have one /CS pin low at any given time so only one ADC will be driving the DOUT line and so there will be no contention on the DOUT line. The microcontroller is controlling the decoder (not shown in diagram) and so it knows which ADC is selected at any given time.
(Editor's note: First line said low)
ok i now understand your point but the main question is while doing such thing regarding the DRDY pin ..........
the DRDY pin gets low after the conversion is available and will be waiting to be read but by this way it will not be read immediately after it gets low there will be some lagging time due to the presence of multiple ADCs but will that be ok with the AD719X ?
waiting for the DRDY pin to get low for 10 ADCs will vary the lagging time between waiting for the DRDY to get low and reading the data......aren't there a maximum time between these two actions and the data will then be lost after?
Yes that is correct - there is a maximum time between the /RDY going low and reading the data before it is lost. The data must be read a small time before the next /RDY signal. This is because /RDY goes high to indicate that a new conversion is about to complete and the data register will be updated shortly. This time is determined by the output data rate.
The best way to ensure that no data is lost when using multiple ADCs is to synchronise the ADCs using the SYNC pin. The /RDY signal for all ADCs will then go low at the same time and you can cycle between all ADCs reading the data. As long as you can read the data from all ADCs quickly enough and without violating the maximum SCLK frequency spec then you will not lose any data. This depends on what speed you wish to operate the ADC.
It should be noted that the AD719x can quickly multiplex the input channels to the ADC and so it would be possible that instead of slowly sampling multiple channels using multiple ADCs you could use a single ADC and quickly multiplex the inputs. There are tradeoffs to this approach but it may be a suitable option depending on your application.
For information on channel switching with the AD719x family see application note AN-1084.
Where is the maximum SCLK frequency specified?
the max SCLK frequency specified is 5 MHz.
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