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AD9970 : Please confirm describe of "DC restore"

Question asked by aimPoint on Jul 28, 2015
Latest reply on Aug 5, 2015 by aimPoint

Hi all

 

I confirmed a data sheet of AD9970 about "DC restore".

I have two question as below.

 

(1)

The block diagram of the AD997x series has difficulty in understanding.

May I understand with structure same as block diagram of ADDI9008?

[attached: Block diagram comparison]

AFE_Block diagram comparison.jpg

 

(2)

I discovered the possibility that register designation in the "DC restore" explanation was wrong.

I extract below an applicable description.


----------< extract form ADDI9008 Datasheet >----------

ADDI9008 datasheet  Rev. SpA | Page 42 of 84

DC Restore

To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 μF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.3 V (AVDD − 0.5 V), so that it is compatible with the 1.8 V supply voltage of the ADDI9008. The dc restore switch is turned on at the SHPNEGLOC edge location and turned off at the SHPLOC edge location.

 

The dc restore circuit can be disabled when the optional PBLK signal is used to isolate large-signal swings from the CCD input (see the Analog Preblanking section). Bit 2 of Address 0xC000 controls whether the dc restore is active during the PBLK interval.

< extract from register table  >

0xC000  [2]  DCBYP           DC restore control.

 

----------< extract from AD9970 Datasheet >----------

AD9970 datasheet  Rev. SpD | Page 36 of 56

DC Restore

To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 μF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.3 V (AVDD-0.5V) to be compatible with the 1.8 V core supply voltage of the AD9970. The dc restore switch is active during the SHP sample pulse time.

 

The dc restore circuit can be disabled when the optional PBLK signal is used to isolate large signal swings from the CCD input (see the Analog Preblanking section). Bit 6 of Address 0x00 controls whether the dc restore is active during the PBLK interval.

< extract from register table  >

0x00  [6]   PBLK_LVL           PBLK level control 

0x00  [7]   DCBYP                DC restore circuit control

 

Bit6 is Typo of Bit7?

 

Best Regards

aimPoint

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