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ad9467_fmc IDELAY Clock

Question asked by wmaguire on Jul 24, 2015
Latest reply on Jul 27, 2015 by wmaguire

Hi all,


I note in the design that the IDELAY clock is set to 200MHz.  However, the ADC can be clocked at 250MHz.  Does the IDELAY clock not need to be a higher speed than the sampling clock as otherwise would the delay not be greater than the clock period?


I suppose if the delay was 1/N DELAY clocks, where N is the delay specified then it would work.