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Clocking the DMA data output to the AD9122

Question asked by tjdub21 on Jul 23, 2015
Latest reply on Jul 30, 2015 by AdrianC

Hello,

 

I am using the KC705 for the FMCOMMS1 reference design. I would like to modify the block diagram to match my needs which are:

 

1) I need to write data to memory

2) I need to pull that data from memory with the DMA controller that feeds to the AD9122 DAC.

3) I need to clock my output data from the DAC at a given clock (SCLK).

 

I have used the reference design to write to the memory using the dac_dma_setup() function in SDK. I have attempted to make modifications to the block diagram to use my SCLK to clock the data that is read from memory and fed to the DAC but I have been unsuccessful.

 

In summary, I would like to pull data from the DMA data at the rate of SCLK (my signal) and output at that rate from the DAC. Is there a way for me to do this by modifying the block diagram in Vivado? I have modified the original FMCOMMS1 block diagram and it is attached.

 

In the block diagram I have fed my SCLK signal to the fifo_rd_clk on the AD9122_dma IP block and to the output dac_clk signal. I was hoping that this would work but it did not.

 

Thanks and if you have any questions then let me know!

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