AnsweredAssumed Answered

configuring AD7682

Question asked by David6 on Jul 23, 2015
Latest reply on Jul 26, 2015 by KarenNE

Background/Use case:

4 analog sensors

  • - AC output range of ~+/- 0.5Vpk-pk
  • - DC offset of 1.65V
  • - Output impedance ~ 32kΩ +/- 8kΩ
  • - Output drives ADA4841-x buffers, which drive ADC inputs CH1-4
  • - sampled at 800 Sa/s
  • - 4 Sensor star grounds short to system ground (GND) at ADC COM pin
  • - 4 Sensors must be sampled with synchronous clocks

AD7682 set up

  • - Digital rail is derived from system 3.3V LDO into VDD and VIO pins
  • - External reference at 3.3V, derived from system 3.3V LDO digital rail, pi filtered, internally buffered, 10uF cap on REF pin, 100nF cap on REFIN pin
  • - CFG register,
    • INCC = Unipolar or Bipolar (TBD) referenced to COM
    • Inx = 11b (CH3)
    • BW = 0 (1/4 BW)
    • REF = 111b (Ext ref, internal buffer, temp disabled)
    • SEQ = 11b (Sequencer enabled, scan IN0 to IN3)
    • RB = 0 (do not read back)
  • - SPI timing in RAC mode, sequencer enabled, with busy indicator
  • - CH 1-4 sampled in continuous mode

 

  1. Based on this excerpt from the data sheet for the AD7682: “digital activity occurs only prior to the safe data reading/writing time, tDATA, because the AD7682/AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From tDATA to tCONV, there is no error correction, and conversion results may be corrupted. Configure the AD7682/AD7689 and initiate the busy indicator (if desired) prior to tDATA.” … This indicates to operate the ADC in RAC mode for best performance, correct?
  2. Do not fully understand the busy indicator … comparing timing diagram in Figure 40 to Figure 39 for RAC, it appears the SDO goes low to indicate host should write conf reg and read data, and the quiet time is over
  3. Does the host need to continuously write the CFG register… I would assume not if it does not need to change
  4. Is it correct that the conversion time is fixed?
  5. How can I control the conversion time?
  6. If possible to slow conversion time, will this minimize noise by running as slow as possible?
  7. Using the EVAL-AD76MUXEDZ and EVAL-CED1Z, is it possible to capture continuous data and save it to file for post processing and analysis?
  8. Referring to Figure 40… to run in RAC mode, 4 CH sequencer enabled, with busy indicator… I made this list of SPI events psuedocode, please review
  9. HOST POR

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv(n-2)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA(x))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv(n-1)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+1)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA(x))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH0(n)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+2)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH0 (n))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH1(n+1)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+3)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH1 (n+1))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH2(n+2)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+4)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH2 (n+2))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH3(n+3)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+5)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH3 (n+3))

 

  1. HOST SS to AD7682 CNV: 0 -> 1 SOC (start Tconv CH0(n+4)), hold for min 10ns
  2. HOST SS to AD7682 CNV: 1 -> 0 (must before AD7682 asserts busy indicator)
  3. AD7682 SDO: HIZ -> 0 (busy indicator) EOC
  4. HOST SCK to AD7682 SCK: 17 CLKs
    1. HOST MOSI to AD7682 DIN (CFG(n+6)) (sequencer enabled)
    2. AD7682 SDO to HOST MISO (DATA CH0 (n+4))

ETC...

Outcomes