Is there a limit to number of instance of AD9361 IP in a design?
Short answer: No
Long answer: No, but eventually you'll run out of resources in the FPGA, so the number of instances is limited by the number of logic block, clock and IO resources in the FPGA. Those numbers do vary a lot between different FPGA variants.
So the 3 I'm using should be ok. Just having issues with my Vivado design and wanted to check.
Can you tell me if there is a simple way to limit the quantization of recorded data? Eg; If I only need to receive 4 bits of I/Q rather than 12 and want to reduce bandwidth.
The AD9361 always outputs 12-bit. The only thing you could do is to throw away the data you don't need after the interface block by adding a custom IP between the interface block and the DMA.
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