Hello, I am working on interfacing an AD9154 FMC card with a Xilinx ZC706 over JESD204 Subclass 1. I have the DAC setup and am able to talk to it over JESD (I have good values on SYNC, FRAMESYNC, and INITIALLANESYNC), however I cannot get a good checksum. I narrowed the problem down to three registers (0x406, 0x408, 0x409).
On the FPGA I have the M value set to 0x3, but when I read the M_RD register (0x406) on the DAC it comes out as 0x1C. I have tried different M values and have found that if the number is a 1,2 or 4, then I get the correct value on the DAC; it appears the problem only exists with the number 0x3.
This oddity also exists on registers 0x408 and 0x409. For the SUBCLASSV_RD portion of 0x408 I get a C instead of a 2, and for the JESDV_RD portion of 0x409 I also get a C instead of 2. The lower portions of these registers reflect the correct values.
Finally, the DAC says it is receiving a checksum value of 0xB5, but when I check the value coming out of the JESD block, I get a value of 0x4A.
In Vivado I have debugged the lanes coming out of the JESD block and going into the JESD_PHY block. I decoded an ILAS frame myself and found that the correct values are coming out of the JESD block, so it appears the problem exists somewhere between the transceivers and the DAC.
Can anyone provide insight to this problem?