We are developing a project based on the ADF4351 PLL; the component is part of a DVB modulator and its layout is similar to the Direct Conversion Modulator shown in Fig 34 of the ADF4351 Data Sheet.
I’m involved in the validation stage of the modulator board. The image attached represents the Modulation Error Ratio as a function of frequency, with a step of 1 MHz, measured with Rohde-Schwarz FSP. We are mainly interested in the performance between 1.8 and 3.2 GHz, where the modulator is supposed to work.
This figure shows a strong degradation between 2890 and 2900 MHz and a trend of degradation that is similar to a saw-tooth in different frequency ranges.
The board has been designed with a 3-pole passive Loop filter, the reference frequency is 16 MHz, the cp current is 5 mA, the loop bandwidth is near 60 kHz. The channel spacing has been set to 10 kHz (too fine for the application – this could be a source of spurs in fractional-N operation, correct?). A sketch of the project made with ADIsimPLL is attached. The reference phase noise in not included in the model, I haven't already learned how to put this effect in the model. The reference used is the ASTX-H11 clock.
I’m almost a complete novice in PLL design and validation, however, using the Evaluation board program for programming registers and ADIsimPLL, some concepts are becoming more familiar.
I would expect a progressive degradation of MER with increasing frequency, not a trend like the one we measured. After some measurements on the output of the PLL, the PLL seems to be the source of degradation. In particular, at 2 GHz (VCO freq = 4 GHz) we found a RMS jitter of 0.79 ps; at 2890 (vco freq 2890) the RMS jitter is equal to 4.15 ps. The integration is performed between 100 Hz and 10 MHz and the measure was performed with Rohde Schwarz FSP. In particular, because the DVB signal is 8 MHz wide, how far from the center frequency should I look at phase noise? At an offset of at least 4 MHz?
Observing the graph in Fig.21 of the ADF4351 Datasheet, it seems that we are following the characteristic of the VCO sensibility (kv in MHz/V). The strong steps in the MER performance are very near to the transitions of the 3 VCOs present in the component. Moreover We observed that the Hole of performance between 2890 and 2900 MHz is moving. So, if I program the registers consecutively with the same values, I obtain different performance, because it seems that the band select process switches sometimes on one VCO, sometimes on the other adjacent VCO and performance changes accordingly. A similar phenomenon can be observed near 1800/1900 MHz, where the VCO is working at 3600 / 3800 MHz, and one again, in this interval a transition of the VCO behavior is observed.
Is this a problem of loop filter project? From what I understand with so little study: small bandwidth means less noise from reference but more noise from VCO, and vice/versa. The design of the loop filter was not my responsibility, I found it already designed.
Moreover, after properly understanding this effect, how can we manage to reduce its impact? We would like to make the MER curve as flat as possible in the range 1.8 – 3.2 GHz, or at least to work well in two ranges centered near f1 = 2.2 GHz and f2 = 2.9 GHz. Starting with the default ADIsimPLL project of the loop filter could be already a good solution?
If the hardware could not be touched, is there an optimum register configuration that can ease the impairment and optimize performance?
Thanks a lot for Your kind help, and sorry for my flat English.