Quick question here, for the AD9915, when setting the lower and upper limits for (for example) a ramp in frequency, they are stored in 32 bit registers but i'm not sure if the units are ever specified?
DRG Limit Control
The ramp accumulator is followed by limit control logic that enforces an upper and lower boundary on the output of the ramp generator. Under no circumstances does the output of the DRG exceed the programmed limit values while the DRG is enabled. The limits are set through the 64-bit digital ramp limit register. Note that the upper limit value must be greater than the lower limit value to ensure normal operation.
It mentions above in the manual:
Note that the frequency units are the same as those used to represent fSYSCLK (MHz, for example). The amplitude units are the same as those used to represent IFS, the full-scale output current of the DAC (mA, for example).
However it appears to me that this is referring to the units on the frequency step size of the ramp, not necessarily the units of the limits. Can somebody clarify?
Additionally, is there any limitation as far as using the boards PLL to generate the system clock before using the DRG? The manual doesn't seem to mention any.