How to program AD9956 registers in Linear Sweep Mode and how to calculate the value of RDFTW,FDFTW,RSRR,FSRR?
The AD9956 has independent rising and falling slope adjustments in linear sweep mode.
Rising slope, meaning when profile pin 0 (PS0) is high, the output frequency is increasing.
Falling slope, meaning when PS0 is low, the output frequency is decreasing.
The rising frequency (PS0= 1) step size = RDFTW (decimal) / 2^32 * the system clock rate.
The falling frequency (PS0=0) step size = FDFTW / 2^32 * the system clock rate.
The rising ramp rate = RSRR (decimal) / 2^16 * SYNC_CLK.
The falling ramp rate = FSRR / 2^16 * SYNC_CLK.
The max system clock is 400MSPS.
The SYNC_CLK = system clock / 4.
To place the device in linear sweep mode see steps below.
Set the linear sweep enable bit in register 0x00h to logic high.
Load the rising frequency step size in register 0x02h
Load the falling frequency step size iin register 0x03h
Load the rising ramp rate in register 0x04h
Load the falling ramp rate in register 0x05h
Load the lower frequency limit in register 0x06h
Load the upper frequency limit in register 0x07h
The lower and upper frequencies determines the bounds of the sweep.
After those values are enter the frequency sweep should be initiated by the PS0 pin.
How come the rising frequency step size=RDFTW/2^32*the system clock? There is no 32-bit register in the AD9956 datasheet. Is it 48, the number of FTW register? Or 24, the number of RDFTW bits?
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