We are using AD9874 IF Digitizing Sub System from ADI in our Airborne Radio for VDB (D8PSK) signals.
When we do slot to slot testing, receiver is not accepting low power messages for signal conditions where the power level swings from -75 dBm to +15 dBm (at input of AD9874) in one slot gap (~1.3 mSec) interval . If the time between these swings is increased to over 5 seconds then the low power signal is received. As the max allowed input signal at input of AD9874 is -18dBm, with +15dBm, the chip is enters saturation. when the slot to slot time difference is 1.3ms (+15dbm and -75dBm swings). But receiver is receiving low level signals when slot to slot difference is more i.e. 5sec.
Please let us know, what is the chip recovery time from its saturation to normal operation.