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ADV7612 color smearing issue in 576i50 mode.

Question asked by Aphraton on Jul 20, 2015
Latest reply on Jul 30, 2015 by GuenterL

Hello!

 

I have an issue with ADV7612 only in 576i50 mode.

In 1080i50 mode ther is no such issue.

It looks like some kind of color smearing common to analog TV when Luma and Chroma are misaligned.

The yellow markings in the pictures below illustrate it.

Please give me a hint - what can be the cause of this issue?

All ADV7612 settings are made as recommended.

 

i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xFF,0x80 ); // I2C Reset
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xFD,0x44 ); // CP
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xFA,0x6C ); // EDID
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xF9,0x64 ); // KSV
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xFB,0x68 ); // HDMI
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0xF8,0x4C ); // DPLL

 

i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x00,0x01 );  // 576i
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x01,0x15 ); // Prim_Mode =101b HDMI-COMP 50Hz
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x02,0xF5 ); // CSC
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x03,0x01 );  // 10-bit SDR ITU-656 mode
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x04,0x60 ); // OP_CH_SEL + 27MHz
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x0B,0x44 ); // Power up part
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x0C,0x42 ); // Power up part
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x14,0x7F ); // Max Drive Strength
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x15,0x80 ); // Disable tristate
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x19,0xC3 );  // LLC DLL phase
i2c_write(I2C_OPENCORES_0_BASE, 0x98>>1,0x33,0x40 ); // LLC DLL Enable
i2c_write(I2C_OPENCORES_0_BASE, 0x44>>1,0xBA,0x01 ); // Set HDMI FreeRun
i2c_write(I2C_OPENCORES_0_BASE, 0x4C>>1,0xB5,0x02 ); // MCLK=384x48kHz

 

i2c_write(I2C_OPENCORES_0_BASE, 0x64>>1,0x40,0x81 ); // Disable HDCP 1.1 features
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x9B,0x03 ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x00,0x09 ); // Set HDMI input Port B (BG_MEAS_PORT_SEL = 001b)
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x02,0x03 ); // Enable Ports A & B in background mode
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x83,0xFC ); // Enable clock terminators for port A & B
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x6F,0x08 ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x85,0x1F ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x87,0x70 ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x8D,0x04 ); // LFG Port A
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x8E,0x1E ); // HFG Port A
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x1A,0x8A ); // unmute audio
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x57,0xDA ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x58,0x01 ); // ADI recommended setting
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x75,0x10 ); // DDC drive strength
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x90,0x04 ); // LFG Port B
i2c_write(I2C_OPENCORES_0_BASE, 0x68>>1,0x91,0x1E ); // HFG Port B

 

screenshot1.bmp

screenshot2.bmp

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