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AD9122 multichip synchronization Frame signal

Question asked by Chris449 on Jul 17, 2015
Latest reply on Jul 20, 2015 by Biao.H

Dear all,


I would like to synchronize two AD9122 which are on two different similar PCBs.

  1. I am sharing the reference clock from the FPGA to the two boards
  2. From the FPGA reference clock, a PLL and the AD9516-0 on each board generate the DACCLK and DAC_REFCLK
  3. I use a SYNC signal to time synchronized/aligned the two AD9516-0
  4. Data in word mode (no frame signal needed)
  5. Synchronization with direct clocking in FIFO rate mode synchronization
  6. Fdata = 122.88MHz, Interpolation x8, DACCLK = 983.04MHz and DAC_REFCLK=Fdata/(8.2^N)=15.36MHz

After reading the datasheet Multichip synchronization section and the AN-1093, something is not clear for me and I have a question about the FRAME signal.


Should it go high for only once to reset the FIFO once and whenever we want to?

Or Should it be periodic as stated in in table 3 of the application note AN-1093, frame clock rate? In that case, I dont really understand the process.


Thanks for your help.