I'm attempting to configure an eval-AD7181C using an FPGA. I'm sending the "##CP XGA 1024x768## :RGB 1024x768 _@ 60Hz 12-Bit DDR 65.000MHz Out through HDMI:" script from ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt. Using ADV Register Control 3.56, I can see that all of the registers loaded by the script have the correct values, but register 0x10 bit 0, IN_LOCK is 0. Register 0x13 bit 4, SD_OP_50Hz, is 1 indicating a 50Hz input. The input is 60Hz. If I then configure from ADV Reg Ctrl, the chip gains lock and works. SD_OP_50Hz is still set.
Ideas about what I'm missing?