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AD9625 : JESD204B Logical Lane Mapping

Question asked by SCO on Jul 16, 2015
Latest reply on Jul 21, 2015 by IanB

Hello,

When AD9625 is used in Single DDC high BW mode (0x82).

Capture_DDCMode.PNG

Are data going out from GTX in the following order ?

 

Lane 0 : I0[N]LSB / I0[N]MSB / Q0[N]LSB / Q0[N]MSB

Lane 1 : I1[N]LSB / I1[N]MSB / Q1[N]LSB / Q1[N]MSB

 

 

Best regards,

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