AnsweredAssumed Answered

axi_ad9361 Xilinx core

Question asked by ltechief55 on Jul 15, 2015
Latest reply on Jul 15, 2015 by rejeesh

Is there a fixed relationship between the rx_samp_freq chosen and the i_clk port of the axi_ad9361? If I want to do additional DSP processing on the FPGA fabric, I would like to know how to clock it. If I set 61.44 MHz, what is the i_clk output port clock?

Outcomes