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ADC clock- jitter vs clock phase-noise

Question asked by burnbush on Apr 18, 2011
Latest reply on Jun 7, 2011 by burnbush

Phase jitter is expressed in a number of radians "RMS" phase jitter (time domain) within a band of frequencies.

For ADC clock specifications. An important ant performance parameter is:  clock jitter expressed using, "(x)ns or (x)fs vs.  S/n ratio.


Note: BTW: (x)fs specs would seem obtainable except by very high grade X-stal source, pricy?    The frequency of the clock is important. A higher frequency clock is more susceptible to jitter (frequency domain 6dB/octave degradation, jitter follow suit.


My question is the ADC people don't specify the bandwidth used for this rms(Jitter) calculations (or do they care)?


If I take the same clock say “ultra low noise synthesizer _ X-stal _ Saw the jitter goes down as I bandlimit the wideband noise.

Which means I have to filter the oscillators output to obtain the desired jitter? despite its  excellent phase noise to limit the wideband constant flat noise.


Apologies as-if required. I'm looking at this from a designed of synthesizers - VCO's. I do interface to ADC but more of a novice here..


Thank you most kindly,


Jim Carlini  RF Engineer