A customer asked:
Following technical discussion, it has been confirmed that AD9250 is supporting JESD204B Subclass1, with SYSREF, it means perfect synchro could be achieved between 2 AD9250.
1. Given AD-FMCJESDADC1-EBZ and Xilinx JESD204 core, does ADI have a demo/ reference design showcasing JESD204B Subclass 1 with perfect multichip synchronization between the 2xAD9250 ? If yes, could you refer me to right resources. Do we have an app note summarizing how syncro between the two ADCs can be achieved using AD-FMCJESDADC1-EBZ?
2. The customer as it has come via EBV is inclined more towards the development on Point 1 but with AD-FMCJESDADC1-EBZ and Altera JESD204B core – say Arria V /10, Stratix V etc.). I came across one of their app notes (PFA) ? Any news on Altera’s side concerning potential reference designs in this regard?