My goal is to run a two-way audio conversation on a platform with an ADSP-BF561 and a AD1885.
The Codec is using the sport interface and DMA channel 3 and 4 for receive and transmit. As a test, the interrupt function linked to the transmit channel sends a sine wave to the codec. This worked fine at 8 khz except that there were some glitches in the sound (missing samples) when the Ethernet was active. So I figured, the there might be an interrupt latency problem or a DMA starving. So I ported the Codec-code on the second core and had the same behavior. This result was very unexpected since core B run in its own L1memory and all the DMA transfers were between L1 of core B and the sports fifo. So how the hell can core A affect core B in this manner? I also discovered that when you have an infinite loop with a sequence of accesses to L3 memory, this can totally stop the DMA to L1, but only when you use cache on L3. In fact, you cannot even stop or access core B with the emulator, until you stop core A. I set to corresponding bit to give priority to DMA over the core, but no improvement.
Since this is an older project, I’m still using VISUAL 4.5. Has anybody else processed Audio and Ethernet on the blackfin with this version or a more recent one? Any suggestions?