I am developing an application with MCU LPC1768 communicating to ADE7754 over SPI. ADE is used to only measure RMS current on 3 phases at 230V@50Hz using CTs, thus I only read AIRMS, BIRMS and CIRMS registers with period of 100ms to get the register values that I later convert to mA in the MCU according to steps in the AN-624. The measurement and SPI communication works just fine, but I noticed huge delays after reset of the ADE7754 IC before obtaining correct values in the xIrms registers.
I found that if I reset the ADE7754 using SWRST bit in the OPMODE register, the AIRMS register gives me the following samples:
<< First I get correct samples. >>
1391, 1369, 1353, 1341, 1230,
<< Then I assert SWRST followed by 1ms delay. Then Im getting the following samples .. >>
60932, 47634, 44826, 25738, 8095, 14273, 2730, 520, 99, 16, 3, 0
<< ...until the value in the AIRMS register reaches 0 and stands still that ways for about 4s. >>
0, 0, 0, ... ,
<< Then suddenly correct samples again appear in the AIRMS register. >>
1449, 1259, 1259, 1379, 1532, 1060, ...
The similar happens also for the BIRMS and CIRMS registers.
I also found that if I reset the ADE7754 using RESET pin, the "reset phase" in which the the AIRMS registers value is 0 doesn't lasts for 4s but 24s! Anyway, if I read the STATUS register just after 1ms delay after reset, I can see the RESET bit set suggesting that the IC has been reset. All register configuration of the ADE7754 is left to default.
In the PCB design, the ADE7754 IC is not isolated from any other parts of the PCB, the VAP, VBP, VCP, VN, CF and IRQ pins are left floating, the AVDD and DVDD are connected to the same +5V supply and AGND and DGND are connected to the common GND. The connection is pretty similar to the one shown in the ADE7754 datasheet TPC 10. Test Circuit for Performance Curves except that the RESET pin is not connected to the +5V, but its controlled by the MCU.
My question is - is this a normal behavior? I would expect to see the valid xIRMS register values shortly after the reset and without such unexpected delay preceded by strange descending series of samples.