I am using ADFMCOMMS1 with zedboard. I am reusing the axi_ad9643 module (from the reference design) with my own FPGA design. In the axi_ad9643_if.v file, I see that two data pin modes are supported
1) mux - across clock edges (rising or falling edges), (parallel LVDS)
2) mux - within clock edges (lower 7 bits and upper 7 bits) (channel multiplexed LVDS)
and register 0x0044 bit 0 can be used to choose the mode.
Now, is AD9643 hard wired onto the radio card to work in a particular mode (parallel LVDS or channel multiplexed LVDS) or is it configurable using the registers? What is the default data pin mode of AD9643 on ADFMCOMMS1?