I am using FMCOMMS1 with KC705 carrier board. I customize the reference design. I need to transfer 8 bit data with adc_clk from memory to my custom IP. So I added axi_dmac core with the configurations on the below picture.
It has same configuration with axi_ad9122_dma except C Dma Data Width Dest which I changed from 64 to 8. fifo_rd_clk is tied to adc_clk.
I got the synthesis error as below.
How can I resolve this problem?