Is it possible to use the clock associated with one AD9361 device as a common data clock across multiple devices if all the devices have been synchronised at base-band ?
DATA_CLK signal synchronization depends on how well MCS SYNC lines are matched. The skew in these lines will show up as skew in DATA_CLK signals. If SYNC lines are well matched than clocking in chip data using only one chip's DATA_CLK should work.
Are you trying to save FPGA pins?
Can you elaborate on which clock signal do you want the parts to share?
When synchronized, BBPLLs of the synchronized devices will be in phase and so will be the digital section clocks.
Hi tlili, thanks for your reply, sorry about not being more specific.
I am referring to the clock associated with the data (especially in LVDS mode), ie DATA_CLK_P and DATA_CLK_N on the data sheet. Is this clock synchronised well enough between chips such that one of these clock signals can clock the data from another chip into an FPGA (provided the PCB traces have been length matched ?)
You guessed it ! The chip has alot of pins ! It would be nice if the data could be multiplexed at a higher rate to save a few of them. Am I right in assuming that you can get away without using the control input and outputs ctrl_out and ctrl_in for basic chip functionality. In my understanding they just make it easier to do an external AGC and make it easier to change some settings without needing to use the SPI port ?
CTRL_OUT and CTRL_IN are not required to be connected to a BBP. However, they provide a lot of functionality and features for real time signal monitoring and control.
I would suggest familiarizing yourself with the functionality they provide and deciding if that is something you need in your application. Even if you do not make a direct connection to FPGA pins you can have test points that you could probe during design debug (in the case of CTRL_OUTs).
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