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PLL lock of DDS9910 eval board

Question asked by mikaelis on Apr 13, 2011
Latest reply on May 6, 2011 by mikaelis

Dear forum,


I finally got my AD9910 eval board to lock to a ref_clk of 117mhz and multiply this frequency up to 936mhz (x8). Since I'm a little bit new to PLLs I'm not quite sure if I can further improve the behaviour of the AD9910 by altering the pll loop filter. (I attached a schematic of my loop filter)

Is there an optimal filter design that will result in the best phase noise performance at the output of the ad9910 for a given ref_clk / multiplication factor? (phase noise is the most important thing for me at the moment).


the reason I'm asking is that wenn i display my ref_clk of 117mhz and the fout of the ad9910 of 351mhz on the oscilloscope i have a jitter of several ps between the two signals (i trigger on my 117mhz ref_clk and see that the 351mhz fout is jittering a little bit). I want this jitter to be as small as possible and suspect that i can improve this by improving my pll loop filter


... does anyone have any good ideas or suggestions how to get closer to a *prefect* loop filter for my application?


thanks a lot in advance

regards - mikael