Does the DROVER pin include the data latency (pipeline delay) or does it take X number of SYSCLK cycles from the time that DROVER pin goes low until an valid output?
The DROVER does not include the data latency. So there will be a fixed time between the DROVER signal toggling first and then output frequency reaching the upper or lower limits. That time was not characterized but it should be constant and stable.
Does AD plan on characterizeing this delay? Just wondering because we using this signal to gate a switch on the DDS output. Or is there any other way to create a chirp waveform without the DRG generating a CW signal before and after the chirp?
The time is conditional, it's dependent on the DRG settings. For example, there's combinational logic used to monitor the instantaneous frequency during the sweep as it approaches the frequency limit. This because, the last frequency step may or may not land exactly on the frequency limit value. So, this combinational logic could delay the DROVER +/- one step rate period. However, the time should be fixed for a given set of values (limits, step size, step rate) used.
The only suggestion I have is enabling OSK mode and connecting an inverter between the DROVER output and the OSK input pin. Manual OSK mode will provide a straight on/off kind of response while automatic OSK mode will ramp up/down the amplitude based on register values. Before a sweep starts, the DROVER output will be high (inverter output is low) which will set the output amplitude to 0. When the sweep starts DROVER will go low (inverter output is high) and the output amplitude will turn on. When the sweep finishes DROVER goes back high (inverter output is low) setting the output amplitude back to 0.
The problem with the external switch, as you found out, is that the DROVER signal is arriving before the start and end of the frequency sweep because the DRG has a pipeline delay. The hope with using the OSK feature is that the DROVER signal is going back to the DDS core where the DRG ramp has finished. The shutting off the amplitude I think will then have a similar pipeline delay as the DRG and should appear at the output roughly at the same time, maybe after a few SYNC_CLK periods.
Thanks Kevin, Good suggestion. My only concern is are the delays on the OSK path equal to the delays of the DROVER pin?
Sorry for the delay in responding. I've been communicating with DSB in order to understand a few things and to see if we have any timing specs. Unfortunately, some of these specs, particularly with the setup I proposed, have never been characterized. The only way to know them for sure is to test them ourselves out in the lab. With that, I can only tell you what my guess is.
The first thing I might mention is the matched latency enable bit in CFR2. There is a brief mention in the specs on page 7 that the OSK is tied into the matched latency. However, the question is if there is a pipeline delay from the OSK section to the DAC output, since the method I mentioned before isn't writing new values to the ASF register. If there is no pipeline delay this way then it won't do any better than the external switch method you mentioned before. However, if there is a pipeline delay then setting the matched latency enable bit will help. Then, the effective delay between the DRG and OSK will only be due to the DROVER pin signal and the OSK pin signal.
What my guess is, is that the delay from the DDS core to the DROVER pin is very short. I doubt there's any pipelining here so the delay could be less than 1 SYSCLK period. I also guess the same thing with the delay from the OSK pin back to the DDS core. The main timing issue here though is the signal on the OSK pin will not take effect until the next SYNC_CLK rising edge. So from the start of the frequency sweep with DROVER going low, which should occur on a SYNC_CLK rising edge, I would guess it to be 1 SYNC_CLK period until the output amplitude turns on. At the end of the frequency sweep, depending on when DROVER goes high relative to SYNC_CLK, I would guess it could be 1-2 SYNC_CLK periods delay until the amplitude shuts off. Unfortunately, the only way to verify this is to test it out in the lab.
DSB also had an intersting point; depending on how the no-dwell bits are set will have an affect on how the part operates. A transition on the DRCTL line is needed to start a sweep regardless of the no-dwell mode is used. If both no-dwell bits are cleared, the DRG will sweep in the direction set by the DRCTL line. Once it reaches the upper or lower limit, the DROVER line will go high and the output will stay at that limit until DRCTL changes. The effect this has on the proposed setup is that when the DRG reaches a frequency limit, it will output that frequency for a brief period of time more the programmed step interval.
If only No-Dwell High is set, the part will only do positive ramps initiated by a rising edge on DRCTL. When the DRG reaches the upper limit, it will set DROVER high and the output will snap back to the lower limit. This means that for a brief period of time at the end of the sweep, the part could output the lower frequency limit before the amplitude is shut off.
If only No-Dwell Low is set, the part will only do negative ramps iniated by a falling edge on DRCTL. When the DRG reaches the lower limit, it will set DROVER high and the output will snap back to the upper limit. This means that for a brief period of time at the end of the sweep, the part could output the upper frequency limit before the amplitude is shut off.
If both No-Dwell bits are set, then the DRG is in continuous recirculate mode, IE continuously ramping up, then down, then up etc. Since you suggested you wanted the output amplitude only turned on when ramping, and the part is continuously ramping in this mode, there's no need to shut the output amplitude off. If you still connect DROVER to OSK though, then you would see the amplitude shut off for 1-2 of SYNC_CLKS periods every time the DRG reached an upper or lower limit. This is because DROVER goes high for 2 SYSCLK periods whenever the DRG reaches a limit in this mode.
The most I can suggest is getting an AD9910 evaluation board and testing this out for yourself. I hope this helps.
Thanks Kevin, I just got back from 2 weeks of vacation. I’ll try these suggestions and get back to you.
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