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Avoiding bus contentions on the parallel port ?

Question asked by snoopy on Apr 10, 2011
Latest reply on Apr 13, 2011 by DivyaS

Just looking through the data sheet and reference manuals for the ADSP-21262 part I can't see what mechanisms there are to avoid bus contention using slow devices such as flash RAM with long chip Enable to output High Z time of 15 to 30 nS. The data sheet doesn't seem to specify the maximum time between back to back cycles. If it's only a few peripheral clock cycles then I'm in trouble with the slow devices although I note that EZ-KIT Lite for this device uses an AMD Am29LV081B flash ram which has a maximum 30 nS output enable  to output High Z time of 30 nS so there must be some intrinsic mechanism to avoid bus contention for back to back cycles..

 

Just out of interest the 21362 has additional parallel port bits in the PPCTL register such as the PPFLMD bit which switches between fast SRAM and slow FLASH RAM devices but this is not available for the ADSP-2126x family of devices.

 

regards

david

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