I wan't to write to the DACs without having to wait 1.5us until BUSY goes back high. Is this possible?
You can write to the part at 50MHz so 24 clocks takes 480ns. On the rising edge of SYNC the command is decoded and if it's a write to any of the DAC registers (X,M or C) and internal calculation begins. This calculation works out the code to be loaded to the DAC based on the gain and offset register settings (y=mx+c type calibration) For a single write this takes 1.5us max (t10) and is indicated by BUSY going high.
I've illustrated this with Figure 1 in the attached document.
The calculation is a three stage process with the first 2 stages taking 600ns and the last taking 300ns - hence 1.5us max.
When the first stage is complete (A) it is available for new data. If the second DAC write completes when A is empty then A can begin calculation on the new data while B is working on the A result of the first write. This is shown in figure 2.
In short, as long as the rising edges of SYNC are more than 600ns apart data can be written to the part while BUSY is high.
Using the max speeds, SYNC needs to be high for a minimum 120ns between writes so as not to corrupt the calculations.
Based on the numbers above you could write to 4 channels in 3.78us (264.5KHz)
This doesn't take into the settling time of the DACs.
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