I have a 4 layer board with 4 isolated channels (see attached picture). Each channel uses an ADuM1441 for data (SPI bus) and a TI SN6501 for power (primary is on the common side). The isolated circuits are measuring low voltage analog signals, so noise should be kept to a minimum (e.g. the power supply will be stopped and SPI activity minimised while sampling is taking place).
For any other board (i.e. one without any isolated regions), I would put an edge guard around the perimeter of the board. In this case from what I have read, the critical side is the common region as it has the primary side of the power supplies (and the transmitters of most data channels). I can see several possible places where the edge guard can be put.
1. Around the perimeter of the common area only (probably excluding the right hand edge which is home to one low speed digital chip).
2. As above, but also around each isolated region.
3. Around the whole board, even though it would change from one isolated area to another.
4. Around the whole board but run the common region along the top so as to completely surround the isolated regions.
My impression is that 1 is a good compromise (esp. compared to 2). But would 3 and 4 actually work/help? Is there a better solution?